Do you find it restful to enter a story with a beginning, a middle and an end, or do you prefer the thrill of a headlong dive into the turmoil of the author’s verbal consciousness? Always predictable, a typical  ASIC/FPGA specification our group develops leans toward the former,  the scope telling  you what to expect, the theory of operation unfolding in the implementation description culminating in the total power consumption after a proper traversal of the various time domains.  From the architectural description to the testability section,  a well-written device specification can impart a sense of coherency for you in a pinch, if  in spite of the best intention, you feel detached eating lunch while peering at the monitor to figure out the latest memory technology, DDR4, even when there actually are no needs whatsoever to be more rooted. In that situation, would the following lines make you smile, shaking off the self-imposed solitude to jump sideways onto a swiftly moving URL?

This mathematically intriguing strip has Euler characteristic